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| author | Pablo Mazzini <pmazzini@gmail.com> | 2022-08-22 12:42:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-22 12:42:26 +0100 |
| commit | d7ed3daa838be80ff2d77154a3114535debf98a1 (patch) | |
| tree | 449561e372100c62507b64692e78db76a48c3f8a /dhcpv4 | |
| parent | 9a5f3bbb33dc6fa4e4eb35a702a5fc72feb35dc8 (diff) | |
| parent | de18a9d48e84748150efb41d6ff584f70a807ecb (diff) | |
Merge branch 'master' into lint
Diffstat (limited to 'dhcpv4')
| -rw-r--r-- | dhcpv4/ztpv4/parse_circuitid.go | 2 | ||||
| -rw-r--r-- | dhcpv4/ztpv4/parse_circuitid_test.go | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/dhcpv4/ztpv4/parse_circuitid.go b/dhcpv4/ztpv4/parse_circuitid.go index 13852ea..42f7647 100644 --- a/dhcpv4/ztpv4/parse_circuitid.go +++ b/dhcpv4/ztpv4/parse_circuitid.go @@ -37,6 +37,8 @@ var circuitRegexs = []*regexp.Regexp{ regexp.MustCompile("^Ethernet(?P<slot>[0-9]+)/(?P<port>[0-9]+)$"), // Juniper bundle interface ae52.0 regexp.MustCompile("^ae(?P<port>[0-9]+).(?P<subport>[0-9])$"), + // Ciena interface format + regexp.MustCompile(`\.OSC(-[0-9]+)?-(?P<slot>[0-9]+)-(?P<port>[0-9]+)$`), } // ParseCircuitID will parse dhcpv4 packet and return CircuitID info diff --git a/dhcpv4/ztpv4/parse_circuitid_test.go b/dhcpv4/ztpv4/parse_circuitid_test.go index cec7403..695d331 100644 --- a/dhcpv4/ztpv4/parse_circuitid_test.go +++ b/dhcpv4/ztpv4/parse_circuitid_test.go @@ -89,6 +89,8 @@ func TestParseCircuitID(t *testing.T) { {name: "Juniper Bundle Pattern", circuit: []byte("ae52.0"), want: &CircuitID{Port: "52", SubPort: "0"}}, {name: "Arista Vlan pattern 1 with circuitid type and length", circuit: []byte("\x00\x0fEthernet14:2001"), want: &CircuitID{Port: "14", Vlan: "2001"}}, {name: "juniperEX pattern", circuit: []byte("ge-0/0/0.0:RANDOMCHAR"), want: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}}, + {name: "Ciena pattern 1", circuit: []byte("tt-tt-tttt-6-7.OSC-1-2"), want: &CircuitID{Slot: "1", Port: "2"}}, + {name: "Ciena pattern 2", circuit: []byte("tt-tt-tttt-6-7.OSC-1-2-3"), want: &CircuitID{Slot: "2", Port: "3"}}, } for _, tc := range tt { t.Run(tc.name, func(t *testing.T) { |