diff options
| author | Hariharakumar Narasimhakumar <hana8349@colorado.edu> | 2021-04-20 10:16:29 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-20 17:16:29 +0100 |
| commit | 6bd1ce0fd305ea107d5734a9fac20ca682545dba (patch) | |
| tree | 9e1e1851fa1b53436660a637deba2dc7b50edf46 | |
| parent | c51060810aaab9c8a0bd1b0fcbf72bc0b91e6427 (diff) | |
Adding xe interface format for Juniper qfx to list of circuit regexes (#418)
* Adding xe interface format for Juniper qfx to list of circuit regexes
Signed-off-by: Hariharakumar Narasimhakumar <hhkumar@fb.com>
* Consolidating regexes for et and xe into one entry
Signed-off-by: Hariharakumar Narasimhakumar <hhkumar@fb.com>
Co-authored-by: Hariharakumar Narasimhakumar <hhkumar@fb.com>
| -rw-r--r-- | dhcpv4/ztpv4/parse_circuitid.go | 4 | ||||
| -rw-r--r-- | dhcpv4/ztpv4/parse_circuitid_test.go | 9 |
2 files changed, 8 insertions, 5 deletions
diff --git a/dhcpv4/ztpv4/parse_circuitid.go b/dhcpv4/ztpv4/parse_circuitid.go index 32a17e3..13852ea 100644 --- a/dhcpv4/ztpv4/parse_circuitid.go +++ b/dhcpv4/ztpv4/parse_circuitid.go @@ -17,8 +17,8 @@ type CircuitID struct { } var circuitRegexs = []*regexp.Regexp{ - // Juniper QFX et-0/0/0:0.0 - regexp.MustCompile("^et-(?P<slot>[0-9]+)/(?P<mod>[0-9]+)/(?P<port>[0-9]+):(?P<subport>[0-9]+).*$"), + // Juniper QFX et-0/0/0:0.0 and xe-0/0/0:0.0 + regexp.MustCompile("^(et|xe)-(?P<slot>[0-9]+)/(?P<mod>[0-9]+)/(?P<port>[0-9]+):(?P<subport>[0-9]+).*$"), // Juniper PTX et-0/0/0.0 regexp.MustCompile("^et-(?P<slot>[0-9]+)/(?P<mod>[0-9]+)/(?P<port>[0-9]+).(?P<subport>[0-9]+)$"), // Juniper EX ge-0/0/0.0 diff --git a/dhcpv4/ztpv4/parse_circuitid_test.go b/dhcpv4/ztpv4/parse_circuitid_test.go index d51b075..8c004b0 100644 --- a/dhcpv4/ztpv4/parse_circuitid_test.go +++ b/dhcpv4/ztpv4/parse_circuitid_test.go @@ -18,7 +18,8 @@ func TestMatchCircuitID(t *testing.T) { {name: "juniperQFX pattern", circuit: "et-0/0/0:0.0", want: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}}, {name: "juniperPTX pattern", circuit: "et-0/0/0.0", want: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}}, {name: "Arista pattern", circuit: "Ethernet3/17/1", want: &CircuitID{Slot: "3", Module: "17", Port: "1"}}, - {name: "Juniper QFX pattern", circuit: "et-1/0/61", want: &CircuitID{Slot: "1", Module: "0", Port: "61"}}, + {name: "Juniper QFX pattern et", circuit: "et-1/0/61", want: &CircuitID{Slot: "1", Module: "0", Port: "61"}}, + {name: "Juniper QFX pattern xe", circuit: "xe-0/0/14:2", want: &CircuitID{Slot: "0", Module: "0", Port: "14", SubPort: "2"}}, {name: "Arista Vlan pattern 1", circuit: "Ethernet14:Vlan2001", want: &CircuitID{Port: "14", Vlan: "Vlan2001"}}, {name: "Arista Vlan pattern 2", circuit: "Ethernet10:2020", want: &CircuitID{Port: "10", Vlan: "2020"}}, {name: "Cisco pattern", circuit: "Gi1/10:2020", want: &CircuitID{Slot: "1", Port: "10", Vlan: "2020"}}, @@ -51,7 +52,8 @@ func TestFormatCircuitID(t *testing.T) { {name: "juniperQFX pattern", circuit: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}, want: "0,0,0,0,"}, {name: "juniperPTX pattern", circuit: &CircuitID{Slot: "0", Module: "0", Port: "0"}, want: "0,0,0,,"}, {name: "Arista pattern", circuit: &CircuitID{Slot: "3", Module: "17", Port: "1"}, want: "3,17,1,,"}, - {name: "Juniper QFX pattern", circuit: &CircuitID{Slot: "1", Module: "0", Port: "61"}, want: "1,0,61,,"}, + {name: "Juniper QFX pattern et", circuit: &CircuitID{Slot: "1", Module: "0", Port: "61"}, want: "1,0,61,,"}, + {name: "Juniper QFX pattern xe", circuit: &CircuitID{Slot: "0", Module: "0", Port: "14", SubPort: "2"}, want: "0,0,14,2,"}, {name: "Arista Vlan pattern 1", circuit: &CircuitID{Port: "14", Vlan: "Vlan2001"}, want: ",,14,,Vlan2001"}, {name: "Arista Vlan pattern 2", circuit: &CircuitID{Port: "10", Vlan: "2020"}, want: ",,10,,2020"}, {name: "Cisco Nexus pattern", circuit: &CircuitID{Slot: "1", Port: "3"}, want: "1,,3,,"}, @@ -80,7 +82,8 @@ func TestParseCircuitID(t *testing.T) { {name: "juniperQFX pattern", circuit: []byte("et-0/0/0:0.0"), want: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}}, {name: "juniperPTX pattern", circuit: []byte("et-0/0/0.0"), want: &CircuitID{Slot: "0", Module: "0", Port: "0", SubPort: "0"}}, {name: "Arista pattern", circuit: []byte("Ethernet3/17/1"), want: &CircuitID{Slot: "3", Module: "17", Port: "1"}}, - {name: "Juniper QFX pattern", circuit: []byte("et-1/0/61"), want: &CircuitID{Slot: "1", Module: "0", Port: "61"}}, + {name: "Juniper QFX pattern et", circuit: []byte("et-1/0/61"), want: &CircuitID{Slot: "1", Module: "0", Port: "61"}}, + {name: "Juniper QFX pattern xe", circuit: []byte("xe-0/0/14:2"), want: &CircuitID{Slot: "0", Module: "0", Port: "14", SubPort: "2"}}, {name: "Arista Vlan pattern 1", circuit: []byte("Ethernet14:Vlan2001"), want: &CircuitID{Port: "14", Vlan: "Vlan2001"}}, {name: "Arista Vlan pattern 2", circuit: []byte("Ethernet10:2020"), want: &CircuitID{Port: "10", Vlan: "2020"}}, {name: "Cisco pattern", circuit: []byte("Gi1/10:2020"), want: &CircuitID{Slot: "1", Port: "10", Vlan: "2020"}}, |