1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
|
// Copyright 2019 The gVisor Authors.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "funcdata.h"
#include "textflag.h"
// NB: Offsets are programatically generated (see BUILD).
//
// This file is concatenated with the definitions.
// Saves a register set.
//
// This is a macro because it may need to executed in contents where a stack is
// not available for calls.
//
#define ERET() \
WORD $0xd69f03e0
#define RSV_REG R18_PLATFORM
#define RSV_REG_APP R9
#define FPEN_NOTRAP 0x3
#define FPEN_SHIFT 20
#define FPEN_ENABLE (FPEN_NOTRAP << FPEN_SHIFT)
#define REGISTERS_SAVE(reg, offset) \
MOVD R0, offset+PTRACE_R0(reg); \
MOVD R1, offset+PTRACE_R1(reg); \
MOVD R2, offset+PTRACE_R2(reg); \
MOVD R3, offset+PTRACE_R3(reg); \
MOVD R4, offset+PTRACE_R4(reg); \
MOVD R5, offset+PTRACE_R5(reg); \
MOVD R6, offset+PTRACE_R6(reg); \
MOVD R7, offset+PTRACE_R7(reg); \
MOVD R8, offset+PTRACE_R8(reg); \
MOVD R10, offset+PTRACE_R10(reg); \
MOVD R11, offset+PTRACE_R11(reg); \
MOVD R12, offset+PTRACE_R12(reg); \
MOVD R13, offset+PTRACE_R13(reg); \
MOVD R14, offset+PTRACE_R14(reg); \
MOVD R15, offset+PTRACE_R15(reg); \
MOVD R16, offset+PTRACE_R16(reg); \
MOVD R17, offset+PTRACE_R17(reg); \
MOVD R19, offset+PTRACE_R19(reg); \
MOVD R20, offset+PTRACE_R20(reg); \
MOVD R21, offset+PTRACE_R21(reg); \
MOVD R22, offset+PTRACE_R22(reg); \
MOVD R23, offset+PTRACE_R23(reg); \
MOVD R24, offset+PTRACE_R24(reg); \
MOVD R25, offset+PTRACE_R25(reg); \
MOVD R26, offset+PTRACE_R26(reg); \
MOVD R27, offset+PTRACE_R27(reg); \
MOVD g, offset+PTRACE_R28(reg); \
MOVD R29, offset+PTRACE_R29(reg); \
MOVD R30, offset+PTRACE_R30(reg);
#define REGISTERS_LOAD(reg, offset) \
MOVD offset+PTRACE_R0(reg), R0; \
MOVD offset+PTRACE_R1(reg), R1; \
MOVD offset+PTRACE_R2(reg), R2; \
MOVD offset+PTRACE_R3(reg), R3; \
MOVD offset+PTRACE_R4(reg), R4; \
MOVD offset+PTRACE_R5(reg), R5; \
MOVD offset+PTRACE_R6(reg), R6; \
MOVD offset+PTRACE_R7(reg), R7; \
MOVD offset+PTRACE_R8(reg), R8; \
MOVD offset+PTRACE_R10(reg), R10; \
MOVD offset+PTRACE_R11(reg), R11; \
MOVD offset+PTRACE_R12(reg), R12; \
MOVD offset+PTRACE_R13(reg), R13; \
MOVD offset+PTRACE_R14(reg), R14; \
MOVD offset+PTRACE_R15(reg), R15; \
MOVD offset+PTRACE_R16(reg), R16; \
MOVD offset+PTRACE_R17(reg), R17; \
MOVD offset+PTRACE_R19(reg), R19; \
MOVD offset+PTRACE_R20(reg), R20; \
MOVD offset+PTRACE_R21(reg), R21; \
MOVD offset+PTRACE_R22(reg), R22; \
MOVD offset+PTRACE_R23(reg), R23; \
MOVD offset+PTRACE_R24(reg), R24; \
MOVD offset+PTRACE_R25(reg), R25; \
MOVD offset+PTRACE_R26(reg), R26; \
MOVD offset+PTRACE_R27(reg), R27; \
MOVD offset+PTRACE_R28(reg), g; \
MOVD offset+PTRACE_R29(reg), R29; \
MOVD offset+PTRACE_R30(reg), R30;
//NOP
#define nop31Instructions() \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f; \
WORD $0xd503201f;
#define ESR_ELx_EC_UNKNOWN (0x00)
#define ESR_ELx_EC_WFx (0x01)
/* Unallocated EC: 0x02 */
#define ESR_ELx_EC_CP15_32 (0x03)
#define ESR_ELx_EC_CP15_64 (0x04)
#define ESR_ELx_EC_CP14_MR (0x05)
#define ESR_ELx_EC_CP14_LS (0x06)
#define ESR_ELx_EC_FP_ASIMD (0x07)
#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
/* Unallocated EC: 0x0A - 0x0B */
#define ESR_ELx_EC_CP14_64 (0x0C)
/* Unallocated EC: 0x0d */
#define ESR_ELx_EC_ILL (0x0E)
/* Unallocated EC: 0x0F - 0x10 */
#define ESR_ELx_EC_SVC32 (0x11)
#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
/* Unallocated EC: 0x14 */
#define ESR_ELx_EC_SVC64 (0x15)
#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
#define ESR_ELx_EC_SYS64 (0x18)
#define ESR_ELx_EC_SVE (0x19)
/* Unallocated EC: 0x1A - 0x1E */
#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
#define ESR_ELx_EC_IABT_LOW (0x20)
#define ESR_ELx_EC_IABT_CUR (0x21)
#define ESR_ELx_EC_PC_ALIGN (0x22)
/* Unallocated EC: 0x23 */
#define ESR_ELx_EC_DABT_LOW (0x24)
#define ESR_ELx_EC_DABT_CUR (0x25)
#define ESR_ELx_EC_SP_ALIGN (0x26)
/* Unallocated EC: 0x27 */
#define ESR_ELx_EC_FP_EXC32 (0x28)
/* Unallocated EC: 0x29 - 0x2B */
#define ESR_ELx_EC_FP_EXC64 (0x2C)
/* Unallocated EC: 0x2D - 0x2E */
#define ESR_ELx_EC_SERROR (0x2F)
#define ESR_ELx_EC_BREAKPT_LOW (0x30)
#define ESR_ELx_EC_BREAKPT_CUR (0x31)
#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
#define ESR_ELx_EC_WATCHPT_LOW (0x34)
#define ESR_ELx_EC_WATCHPT_CUR (0x35)
/* Unallocated EC: 0x36 - 0x37 */
#define ESR_ELx_EC_BKPT32 (0x38)
/* Unallocated EC: 0x39 */
#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
/* Unallocted EC: 0x3B */
#define ESR_ELx_EC_BRK64 (0x3C)
/* Unallocated EC: 0x3D - 0x3F */
#define ESR_ELx_EC_MAX (0x3F)
#define ESR_ELx_EC_SHIFT (26)
#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
#define ESR_ELx_IL_SHIFT (25)
#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
/* ISS field definitions shared by different classes */
#define ESR_ELx_WNR_SHIFT (6)
#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
/* Asynchronous Error Type */
#define ESR_ELx_IDS_SHIFT (24)
#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
#define ESR_ELx_AET_SHIFT (10)
#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
/* Shared ISS field definitions for Data/Instruction aborts */
#define ESR_ELx_SET_SHIFT (11)
#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
#define ESR_ELx_FnV_SHIFT (10)
#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
#define ESR_ELx_EA_SHIFT (9)
#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
#define ESR_ELx_S1PTW_SHIFT (7)
#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
#define ESR_ELx_FSC (0x3F)
#define ESR_ELx_FSC_TYPE (0x3C)
#define ESR_ELx_FSC_EXTABT (0x10)
#define ESR_ELx_FSC_SERROR (0x11)
#define ESR_ELx_FSC_ACCESS (0x08)
#define ESR_ELx_FSC_FAULT (0x04)
#define ESR_ELx_FSC_PERM (0x0C)
/* ISS field definitions for Data Aborts */
#define ESR_ELx_ISV_SHIFT (24)
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
#define ESR_ELx_SAS_SHIFT (22)
#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
#define ESR_ELx_SSE_SHIFT (21)
#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
#define ESR_ELx_SRT_SHIFT (16)
#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
#define ESR_ELx_SF_SHIFT (15)
#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
#define ESR_ELx_AR_SHIFT (14)
#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
#define ESR_ELx_CM_SHIFT (8)
#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
/* ISS field definitions for exceptions taken in to Hyp */
#define ESR_ELx_CV (UL(1) << 24)
#define ESR_ELx_COND_SHIFT (20)
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
#define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
#define LOAD_KERNEL_ADDRESS(from, to) \
MOVD from, to; \
ORR $0xffff000000000000, to, to;
// LOAD_KERNEL_STACK loads the kernel temporary stack.
#define LOAD_KERNEL_STACK(from) \
LOAD_KERNEL_ADDRESS(CPU_SELF(from), RSV_REG); \
MOVD $CPU_STACK_TOP(RSV_REG), RSV_REG; \
MOVD RSV_REG, RSP; \
ISB $15; \
DSB $15;
#define SWITCH_TO_APP_PAGETABLE(from) \
MOVD CPU_TTBR0_APP(from), RSV_REG; \
WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
ISB $15; \
DSB $15;
#define SWITCH_TO_KVM_PAGETABLE(from) \
MOVD CPU_TTBR0_KVM(from), RSV_REG; \
WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
ISB $15; \
DSB $15;
#define IRQ_ENABLE \
MSR $2, DAIFSet;
#define IRQ_DISABLE \
MSR $2, DAIFClr;
#define VFP_ENABLE \
MOVD $FPEN_ENABLE, R0; \
WORD $0xd5181040; \ //MSR R0, CPACR_EL1
ISB $15;
#define VFP_DISABLE \
MOVD $0x0, R0; \
WORD $0xd5181040; \ //MSR R0, CPACR_EL1
ISB $15;
#define KERNEL_ENTRY_FROM_EL0 \
SUB $16, RSP, RSP; \ // step1, save r18, r9 into kernel temporary stack.
STP (RSV_REG, RSV_REG_APP), 16*0(RSP); \
WORD $0xd538d092; \ //MRS TPIDR_EL1, R18, step2, switch user pagetable.
SWITCH_TO_KVM_PAGETABLE(RSV_REG); \
WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
MOVD CPU_APP_ADDR(RSV_REG), RSV_REG_APP; \ // step3, load app context pointer.
REGISTERS_SAVE(RSV_REG_APP, 0); \ // step4, save app context.
MOVD RSV_REG_APP, R20; \
LDP 16*0(RSP), (RSV_REG, RSV_REG_APP); \
ADD $16, RSP, RSP; \
MOVD RSV_REG, PTRACE_R18(R20); \
MOVD RSV_REG_APP, PTRACE_R9(R20); \
MOVD R20, RSV_REG_APP; \
WORD $0xd5384003; \ // MRS SPSR_EL1, R3
MOVD R3, PTRACE_PSTATE(RSV_REG_APP); \
MRS ELR_EL1, R3; \
MOVD R3, PTRACE_PC(RSV_REG_APP); \
WORD $0xd5384103; \ // MRS SP_EL0, R3
MOVD R3, PTRACE_SP(RSV_REG_APP);
#define KERNEL_ENTRY_FROM_EL1 \
WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
REGISTERS_SAVE(RSV_REG, CPU_REGISTERS); \ // save sentry context
MOVD RSV_REG_APP, CPU_REGISTERS+PTRACE_R9(RSV_REG); \
WORD $0xd5384004; \ // MRS SPSR_EL1, R4
MOVD R4, CPU_REGISTERS+PTRACE_PSTATE(RSV_REG); \
MRS ELR_EL1, R4; \
MOVD R4, CPU_REGISTERS+PTRACE_PC(RSV_REG); \
MOVD RSP, R4; \
MOVD R4, CPU_REGISTERS+PTRACE_SP(RSV_REG);
TEXT ·Halt(SB),NOSPLIT,$0
// clear bluepill.
WORD $0xd538d092 //MRS TPIDR_EL1, R18
CMP RSV_REG, R9
BNE mmio_exit
MOVD $0, CPU_REGISTERS+PTRACE_R9(RSV_REG)
mmio_exit:
// Disable fpsimd.
WORD $0xd5381041 // MRS CPACR_EL1, R1
MOVD R1, CPU_LAZY_VFP(RSV_REG)
VFP_DISABLE
// MMIO_EXIT.
MOVD $0, R9
MOVD R0, 0xffff000000001000(R9)
B ·kernelExitToEl1(SB)
TEXT ·Shutdown(SB),NOSPLIT,$0
// PSCI EVENT.
MOVD $0x84000009, R0
HVC $0
// See kernel.go.
TEXT ·Current(SB),NOSPLIT,$0-8
MOVD CPU_SELF(RSV_REG), R8
MOVD R8, ret+0(FP)
RET
#define STACK_FRAME_SIZE 16
TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
ERET()
TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
ERET()
TEXT ·Start(SB),NOSPLIT,$0
IRQ_DISABLE
MOVD R8, RSV_REG
ORR $0xffff000000000000, RSV_REG, RSV_REG
WORD $0xd518d092 //MSR R18, TPIDR_EL1
B ·kernelExitToEl1(SB)
TEXT ·El1_sync_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_irq_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_fiq_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_error_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_sync(SB),NOSPLIT,$0
KERNEL_ENTRY_FROM_EL1
WORD $0xd5385219 // MRS ESR_EL1, R25
LSR $ESR_ELx_EC_SHIFT, R25, R24
CMP $ESR_ELx_EC_DABT_CUR, R24
BEQ el1_da
CMP $ESR_ELx_EC_IABT_CUR, R24
BEQ el1_ia
CMP $ESR_ELx_EC_SYS64, R24
BEQ el1_undef
CMP $ESR_ELx_EC_SP_ALIGN, R24
BEQ el1_sp_pc
CMP $ESR_ELx_EC_PC_ALIGN, R24
BEQ el1_sp_pc
CMP $ESR_ELx_EC_UNKNOWN, R24
BEQ el1_undef
CMP $ESR_ELx_EC_SVC64, R24
BEQ el1_svc
CMP $ESR_ELx_EC_BREAKPT_CUR, R24
BGE el1_dbg
CMP $ESR_ELx_EC_FP_ASIMD, R24
BEQ el1_fpsimd_acc
B el1_invalid
el1_da:
B ·Halt(SB)
el1_ia:
B ·Halt(SB)
el1_sp_pc:
B ·Shutdown(SB)
el1_undef:
B ·Shutdown(SB)
el1_svc:
B ·Halt(SB)
el1_dbg:
B ·Shutdown(SB)
el1_fpsimd_acc:
VFP_ENABLE
B ·kernelExitToEl1(SB) // Resume.
el1_invalid:
B ·Shutdown(SB)
TEXT ·El1_irq(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_fiq(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El1_error(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_sync(SB),NOSPLIT,$0
KERNEL_ENTRY_FROM_EL0
WORD $0xd5385219 // MRS ESR_EL1, R25
LSR $ESR_ELx_EC_SHIFT, R25, R24
CMP $ESR_ELx_EC_SVC64, R24
BEQ el0_svc
CMP $ESR_ELx_EC_DABT_LOW, R24
BEQ el0_da
CMP $ESR_ELx_EC_IABT_LOW, R24
BEQ el0_ia
CMP $ESR_ELx_EC_FP_ASIMD, R24
BEQ el0_fpsimd_acc
CMP $ESR_ELx_EC_SVE, R24
BEQ el0_sve_acc
CMP $ESR_ELx_EC_FP_EXC64, R24
BEQ el0_fpsimd_exc
CMP $ESR_ELx_EC_SP_ALIGN, R24
BEQ el0_sp_pc
CMP $ESR_ELx_EC_PC_ALIGN, R24
BEQ el0_sp_pc
CMP $ESR_ELx_EC_UNKNOWN, R24
BEQ el0_undef
CMP $ESR_ELx_EC_BREAKPT_LOW, R24
BGE el0_dbg
B el0_invalid
el0_svc:
B ·Halt(SB)
el0_da:
B ·Halt(SB)
el0_ia:
B ·Shutdown(SB)
el0_fpsimd_acc:
B ·Shutdown(SB)
el0_sve_acc:
B ·Shutdown(SB)
el0_fpsimd_exc:
B ·Shutdown(SB)
el0_sp_pc:
B ·Shutdown(SB)
el0_undef:
B ·Shutdown(SB)
el0_dbg:
B ·Shutdown(SB)
el0_invalid:
B ·Shutdown(SB)
TEXT ·El0_irq(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_fiq(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_error(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_sync_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_irq_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_fiq_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·El0_error_invalid(SB),NOSPLIT,$0
B ·Shutdown(SB)
TEXT ·Vectors(SB),NOSPLIT,$0
B ·El1_sync_invalid(SB)
nop31Instructions()
B ·El1_irq_invalid(SB)
nop31Instructions()
B ·El1_fiq_invalid(SB)
nop31Instructions()
B ·El1_error_invalid(SB)
nop31Instructions()
B ·El1_sync(SB)
nop31Instructions()
B ·El1_irq(SB)
nop31Instructions()
B ·El1_fiq(SB)
nop31Instructions()
B ·El1_error(SB)
nop31Instructions()
B ·El0_sync(SB)
nop31Instructions()
B ·El0_irq(SB)
nop31Instructions()
B ·El0_fiq(SB)
nop31Instructions()
B ·El0_error(SB)
nop31Instructions()
B ·El0_sync_invalid(SB)
nop31Instructions()
B ·El0_irq_invalid(SB)
nop31Instructions()
B ·El0_fiq_invalid(SB)
nop31Instructions()
B ·El0_error_invalid(SB)
nop31Instructions()
// The exception-vector-table is required to be 11-bits aligned.
// Please see Linux source code as reference: arch/arm64/kernel/entry.s.
// For gvisor, I defined it as 4K in length, filled the 2nd 2K part with NOPs.
// So that, I can safely move the 1st 2K part into the address with 11-bits alignment.
WORD $0xd503201f //nop
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
WORD $0xd503201f
nop31Instructions()
|
