diff options
| author | gVisor bot <gvisor-bot@google.com> | 2019-12-26 13:42:39 -0800 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2019-12-26 13:42:39 -0800 |
| commit | 7b5a59d5038df65a3d5ebb6a24e6b8a2aaa898ab (patch) | |
| tree | c5272e2fb1151e57a3a8b4b066c1db5daa834d33 /pkg | |
| parent | 87e4d03fdf576348ac7023c599e0fc66ad4cccbd (diff) | |
| parent | 7b83d21856e569742397ab8b0146910eeff1462f (diff) | |
Merge pull request #1460 from lubinszARM:pr_clean_code1
PiperOrigin-RevId: 287221280
Diffstat (limited to 'pkg')
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_arm64.s | 4 | ||||
| -rw-r--r-- | pkg/sentry/platform/ring0/lib_arm64.s | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/pkg/sentry/platform/ring0/entry_arm64.s b/pkg/sentry/platform/ring0/entry_arm64.s index add2c3e08..813ef9822 100644 --- a/pkg/sentry/platform/ring0/entry_arm64.s +++ b/pkg/sentry/platform/ring0/entry_arm64.s @@ -554,6 +554,10 @@ TEXT ·Vectors(SB),NOSPLIT,$0 B ·El0_error_invalid(SB) nop31Instructions() + // The exception-vector-table is required to be 11-bits aligned. + // Please see Linux source code as reference: arch/arm64/kernel/entry.s. + // For gvisor, I defined it as 4K in length, filled the 2nd 2K part with NOPs. + // So that, I can safely move the 1st 2K part into the address with 11-bits alignment. WORD $0xd503201f //nop nop31Instructions() WORD $0xd503201f diff --git a/pkg/sentry/platform/ring0/lib_arm64.s b/pkg/sentry/platform/ring0/lib_arm64.s index 1c9171004..0e6a6235b 100644 --- a/pkg/sentry/platform/ring0/lib_arm64.s +++ b/pkg/sentry/platform/ring0/lib_arm64.s @@ -12,12 +12,15 @@ // See the License for the specific language governing permissions and // limitations under the License. +#include "funcdata.h" +#include "textflag.h" + TEXT ·CPACREL1(SB),NOSPLIT,$0-8 WORD $0xd5381041 // MRS CPACR_EL1, R1 MOVD R1, ret+0(FP) RET -TEXT ·FPCR(SB),NOSPLIT,$0-8 +TEXT ·GetFPCR(SB),NOSPLIT,$0-8 WORD $0xd53b4201 // MRS NZCV, R1 MOVD R1, ret+0(FP) RET @@ -27,7 +30,7 @@ TEXT ·GetFPSR(SB),NOSPLIT,$0-8 MOVD R1, ret+0(FP) RET -TEXT ·FPCR(SB),NOSPLIT,$0-8 +TEXT ·SetFPCR(SB),NOSPLIT,$0-8 MOVD addr+0(FP), R1 WORD $0xd51b4201 // MSR R1, NZCV RET |