diff options
author | gVisor bot <gvisor-bot@google.com> | 2019-06-02 06:44:55 +0000 |
---|---|---|
committer | gVisor bot <gvisor-bot@google.com> | 2019-06-02 06:44:55 +0000 |
commit | ceb0d792f328d1fc0692197d8856a43c3936a571 (patch) | |
tree | 83155f302eff44a78bcc30a3a08f4efe59a79379 /pkg/atomicbitops/atomic_bitops_amd64.s | |
parent | deb7ecf1e46862d54f4b102f2d163cfbcfc37f3b (diff) | |
parent | 216da0b733dbed9aad9b2ab92ac75bcb906fd7ee (diff) |
Merge 216da0b7 (automated)
Diffstat (limited to 'pkg/atomicbitops/atomic_bitops_amd64.s')
-rw-r--r-- | pkg/atomicbitops/atomic_bitops_amd64.s | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/pkg/atomicbitops/atomic_bitops_amd64.s b/pkg/atomicbitops/atomic_bitops_amd64.s new file mode 100644 index 000000000..db0972001 --- /dev/null +++ b/pkg/atomicbitops/atomic_bitops_amd64.s @@ -0,0 +1,115 @@ +// Copyright 2018 The gVisor Authors. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// +build amd64 + +#include "textflag.h" + +TEXT ·AndUint32(SB),$0-12 + MOVQ addr+0(FP), BP + MOVL val+8(FP), AX + LOCK + ANDL AX, 0(BP) + RET + +TEXT ·OrUint32(SB),$0-12 + MOVQ addr+0(FP), BP + MOVL val+8(FP), AX + LOCK + ORL AX, 0(BP) + RET + +TEXT ·XorUint32(SB),$0-12 + MOVQ addr+0(FP), BP + MOVL val+8(FP), AX + LOCK + XORL AX, 0(BP) + RET + +TEXT ·CompareAndSwapUint32(SB),$0-20 + MOVQ addr+0(FP), DI + MOVL old+8(FP), AX + MOVL new+12(FP), DX + LOCK + CMPXCHGL DX, 0(DI) + MOVL AX, ret+16(FP) + RET + +TEXT ·AndUint64(SB),$0-16 + MOVQ addr+0(FP), BP + MOVQ val+8(FP), AX + LOCK + ANDQ AX, 0(BP) + RET + +TEXT ·OrUint64(SB),$0-16 + MOVQ addr+0(FP), BP + MOVQ val+8(FP), AX + LOCK + ORQ AX, 0(BP) + RET + +TEXT ·XorUint64(SB),$0-16 + MOVQ addr+0(FP), BP + MOVQ val+8(FP), AX + LOCK + XORQ AX, 0(BP) + RET + +TEXT ·CompareAndSwapUint64(SB),$0-32 + MOVQ addr+0(FP), DI + MOVQ old+8(FP), AX + MOVQ new+16(FP), DX + LOCK + CMPXCHGQ DX, 0(DI) + MOVQ AX, ret+24(FP) + RET + +TEXT ·IncUnlessZeroInt32(SB),NOSPLIT,$0-9 + MOVQ addr+0(FP), DI + MOVL 0(DI), AX + +retry: + TESTL AX, AX + JZ fail + LEAL 1(AX), DX + LOCK + CMPXCHGL DX, 0(DI) + JNZ retry + + SETEQ ret+8(FP) + RET + +fail: + MOVB AX, ret+8(FP) + RET + +TEXT ·DecUnlessOneInt32(SB),NOSPLIT,$0-9 + MOVQ addr+0(FP), DI + MOVL 0(DI), AX + +retry: + LEAL -1(AX), DX + TESTL DX, DX + JZ fail + LOCK + CMPXCHGL DX, 0(DI) + JNZ retry + + SETEQ ret+8(FP) + RET + +fail: + MOVB DX, ret+8(FP) + RET |