From be0897702e77081ce6f1add7b4e98fcfcc020d7e Mon Sep 17 00:00:00 2001 From: howard zhang Date: Fri, 14 May 2021 11:00:36 +0800 Subject: calibrate defaultOverheadCycles for ARM64 Usually ARM counter-timer frequency is range from 1-50Mhz which is much less than that on x86, so we calibrate defaultOverheadCycles for ARM. Signed-off-by: howard zhang --- pkg/sentry/time/sampler_amd64.go | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 pkg/sentry/time/sampler_amd64.go (limited to 'pkg/sentry/time/sampler_amd64.go') diff --git a/pkg/sentry/time/sampler_amd64.go b/pkg/sentry/time/sampler_amd64.go new file mode 100644 index 000000000..72cb74be3 --- /dev/null +++ b/pkg/sentry/time/sampler_amd64.go @@ -0,0 +1,26 @@ +// Copyright 2018 The gVisor Authors. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//+build amd64 + +package time + +const( + // defaultOverheadTSC is the default estimated syscall overhead in TSC cycles. + // It is further refined as syscalls are made. + defaultOverheadCycles = 1 * 1000 + + // maxOverheadCycles is the maximum allowed syscall overhead in TSC cycles. + maxOverheadCycles = 100 * defaultOverheadCycles +) -- cgit v1.2.3