Age | Commit message (Collapse) | Author |
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PiperOrigin-RevId: 351638451
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These are primarily simplification and lint mistakes. However, minor
fixes are also included and tests added where appropriate.
PiperOrigin-RevId: 351425971
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This requires several changes:
* Templates must preserve relevant tags.
* Pagetables templates are split into two targets, each preserving tags.
* The binary VDSO is similarly split into two targets, with some juggling.
* The top level tools/go_branch.sh now does a crossbuild of ARM64 as well,
and checks and merges the results of the two branches together.
Fixes #5178
PiperOrigin-RevId: 351304330
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PiperOrigin-RevId: 350862699
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global
In order to improve the performance, some kpti related codes(TCR.A1) have
been reverted, and set kernel pagetable as global.
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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PiperOrigin-RevId: 347890782
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PiperOrigin-RevId: 347660920
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PiperOrigin-RevId: 347047550
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PiperOrigin-RevId: 346496532
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PiperOrigin-RevId: 346143528
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PiperOrigin-RevId: 346134026
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PiperOrigin-RevId: 344958513
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Add more comments and more handling for exceptions.
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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If no vild syndrome(data abort outside memslots) was reported by kvm, let userspace to do the
ext_dabt injection to bail out this issue.
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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This patch adds support for tlbi-vale1ls/tlbi-aside1ls.
And make the code consistent with the flush strategy of the x86 platform.
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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As PCALIGN is available on golang asm for arm64.
https://golang.org/pkg/cmd/internal/obj/arm64/
No need to use rewriteVectors() to ensure
alignment of exception vector.
Signed-off-by: Howard Zhang <howard.zhang@arm.com>
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PiperOrigin-RevId: 343130667
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PiperOrigin-RevId: 343000335
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Optimize and bug fix all fpsimd related code.
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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I added 2 unified processing functions for all exceptions of el/el0
Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
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feature
Signed-off-by: Robin Luk <lubin.lu@alibaba-inc.com>
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Signed-off-by: Robin Luk <lubin.lu@alibaba-inc.com>
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PiperOrigin-RevId: 341445910
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PiperOrigin-RevId: 340484823
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Use an sErr injection to trigger sigbus when we receive EFAULT from the
run ioctl.
After applying this patch, mmap_test_runsc_kvm will be passed on
Arm64.
Signed-off-by: Bin Lu <bin.lu@arm.com>
COPYBARA_INTEGRATE_REVIEW=https://github.com/google/gvisor/pull/4542 from lubinszARM:pr_kvm_mmap_1 f81bd42466d1d60a581e5fb34de18b78878c68c1
PiperOrigin-RevId: 340461239
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Signed-off-by: Howard Zhang <howard.zhang@arm.com>
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Fixes: #509
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antfin.com>
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
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PiperOrigin-RevId: 339921446
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current when save fpsmid register is using following
instruction:
# FMOVD Fx, 16*1(R0)
this instruction will compiled to:
# str Dx, [x0, #16]
Dx is 64bit fp register not 128bit, then upper 64bit data
will be lossed, this will cause application meet many random
crash issue. need use 128bit register Vx or Q0 to save and
restore the fpsmid context.
Signed-off-by: Min Le <lemin.lm@antgroup.com>
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PiperOrigin-RevId: 339540747
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Signed-off-by: Min Le <lemin.lm@antgroup.com>
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I have added support for setSystemTimeLegacy() by setting cntvoff.
With this pr, TestRdtsc and other kvm syscall test cases(nanosleep,
wait...) can be passed on Arm64.
TO-DO: Add precise synchronization to KVM for Arm64.
Reference PR: https://github.com/google/gvisor/pull/4397
Signed-off-by: Bin Lu <bin.lu@arm.com>
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PiperOrigin-RevId: 338321125
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PiperOrigin-RevId: 338126491
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Consistent with the linux kernel, bad regs.Sp
return SIGSEGV
Signed-off-by: Howard Zhang <howard.zhang@arm.com>
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Consistent with the linux approach, we will produce a sigill to handle
el0_undef.
After applying this patch, exec_binary_test_runsc_kvm will be passed on
Arm64.
Signed-off-by: Bin Lu <bin.lu@arm.com>
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PiperOrigin-RevId: 337544656
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Signed-off-by: Min Le <lemin.lm@antgroup.com>
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PiperOrigin-RevId: 336976081
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PiperOrigin-RevId: 336970511
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PiperOrigin-RevId: 336962937
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The required states may simply not be observed by the thread running bounce, so
track guest and user generations to ensure that at least one of the desired
state transitions happens.
Fixes #3532
PiperOrigin-RevId: 336908216
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PiperOrigin-RevId: 336719900
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The tls of guest-el1-sentry and host-el0-sentry may be different on Arm64.
I added a solution for it.
Signed-off-by: Bin Lu <bin.lu@arm.com>
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Signed-off-by: Min Le <lemin.lm@antgroup.com>
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PiperOrigin-RevId: 336366624
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PiperOrigin-RevId: 336362818
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the correct value needed is 0xbbff440c0400 but the const
defined is 0x000000000000ffc0 due to the operator error
in _MT_EL1_INIT, both kernel and user space memory
attribute should be Normal memory not DEVICE_nGnRE
Signed-off-by: Min Le <lemin.lm@antgroup.com>
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PiperOrigin-RevId: 335930035
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By using TSC scaling as a hack, we can trick the kernel into setting an offset
of exactly zero. Huzzah!
PiperOrigin-RevId: 335922019
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