Age | Commit message (Collapse) | Author | |
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2020-07-13 | Merge release-20200622.1-100-g505b4f5e5 (automated) | gVisor bot | |
2020-07-08 | Merge release-20200622.1-81-gf3fa43cf2 (automated) | gVisor bot | |
2020-07-08 | Merge release-20200622.1-80-ge1f11dea2 (automated) | gVisor bot | |
2020-07-03 | allow guest user applications read ctr_el0 on Arm64 | Bin Lu | |
At present, when doing syscall_kvm test, we need to enable the function of ESR_ELx_SYS64_ISS_SYS_CTR_READ to successfully pass the test. I set SCTLR_EL1.UCT==1, so that the related cases can passed. Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-06-24 | Merge release-20200608.0-119-g364ac92ba (automated) | gVisor bot | |
2020-06-23 | Merge release-20200608.0-108-g44dd65ce1 (automated) | gVisor bot | |
2020-06-16 | support sError injection in kvm module on Arm64 | Bin Lu | |
There are 3 types of asynchronous exceptions on Arm64: sError, IRQ, FIQ. In this case, we use the sError injection method in bluepillHandler to force the guest to quit. So that the test case of "TestBounce" can be passed on Arm64. Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-06-11 | Merge release-20200522.0-127-gb436b9717 (automated) | gVisor bot | |
2020-06-10 | Merge pull request #2711 from lubinszARM:pr_mmio | gVisor bot | |
PiperOrigin-RevId: 315812219 | |||
2020-06-10 | Merge release-20200522.0-115-gf004bb870 (automated) | gVisor bot | |
2020-06-10 | Merge release-20200522.0-114-g9d2b2c121 (automated) | gVisor bot | |
2020-06-10 | Merge release-20200522.0-109-ge3cbfbf34 (automated) | gVisor bot | |
2020-06-09 | minor change in kvm module for Arm64 | Bin Lu | |
Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-06-08 | Merge release-20200522.0-97-gac37979c (automated) | gVisor bot | |
2020-06-08 | Merge release-20200522.0-95-gdc029b4b (automated) | gVisor bot | |
2020-06-07 | Merge release-20200522.0-93-g62603041 (automated) | gVisor bot | |
2020-06-06 | Merge release-20200522.0-91-g427d2082 (automated) | gVisor bot | |
2020-06-06 | Merge release-20200522.0-88-g527d08f6 (automated) | gVisor bot | |
2020-06-05 | Add +checkescape annotations to kvm/ring0. | Adin Scannell | |
This analysis also catches a potential bug, which is a split on mapPhysical. This would have led to potential guest-exit during Mapping (although this would have been handled by the now-unecessary retryInGuest loop). PiperOrigin-RevId: 315025106 | |||
2020-06-01 | Merge release-20200522.0-50-g288a1ca6 (automated) | gVisor bot | |
2020-06-01 | Merge pull request #2689 from lubinszARM:pr_prot_none | gVisor bot | |
PiperOrigin-RevId: 314186752 | |||
2020-05-29 | Merge release-20200522.0-42-g65569cfc (automated) | gVisor bot | |
2020-05-29 | Update Go version build tags | Michael Pratt | |
None of the dependencies have changed in 1.15. It may be possible to simplify some of the wrappers in rawfile following 1.13, but that can come in a later change. PiperOrigin-RevId: 313863264 | |||
2020-05-27 | Merge release-20200518.0-45-g0bc022b7 (automated) | gVisor bot | |
2020-05-17 | adding the VM-Exit method for Arm64 | Bin Lu | |
On amd64, it uses 'HLT' to leave the guest. Unlike amd64, arm64 can only uses mmio_exit/psci to leave the guest. So, I designed the HYPERCALL_VMEXIT to be compatible with amd64/arm64. To keep it simple, I used the address of exception table as the MMIO base address, so that I can trigger a MMIO-EXIT by forcibly writing this space. Then, in host user space, I can calculate this address to find out which hypercall. Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-05-13 | PROT_NONE should be specially treated in the step of mapPhysical | Bin Lu | |
It's a workaround to treat PROT_NONE as RDONLY temporarily. TODO(gvisor.dev/issue/2686): PROT_NONE should be specially treated. Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-05-13 | adding the methods to get/set TLS for Arm64 kvm platform | Bin Lu | |
Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-05-07 | Merge release-20200422.0-51-g1f4087e (automated) | gVisor bot | |
2020-04-26 | Merge release-20200323.0-251-g3c67754 (automated) | gVisor bot | |
2020-04-25 | Enable automated marshalling for signals and the arch package. | Rahat Mahmood | |
PiperOrigin-RevId: 308472331 | |||
2020-04-24 | Merge release-20200323.0-246-g1072547 (automated) | gVisor bot | |
2020-04-24 | Merge pull request #1707 from lubinszARM:pr_lazy_fpsimd_2 | gVisor bot | |
PiperOrigin-RevId: 308347744 | |||
2020-04-23 | Merge release-20200323.0-215-g0c58694 (automated) | gVisor bot | |
2020-04-22 | Specify a memory file in platform.New(). | Andrei Vagin | |
PiperOrigin-RevId: 307941984 | |||
2020-04-18 | Merge release-20200323.0-185-gea9bb1c (automated) | gVisor bot | |
2020-04-17 | Merge pull request #2235 from xiaobo55x:pcid | gVisor bot | |
PiperOrigin-RevId: 307166482 | |||
2020-04-13 | Merge release-20200323.0-138-ge1959f5 (automated) | gVisor bot | |
2020-04-13 | Merge pull request #2321 from lubinszARM:pr_nogo | gVisor bot | |
PiperOrigin-RevId: 306300032 | |||
2020-04-09 | Merge release-20200323.0-107-g9a5e5ab (automated) | gVisor bot | |
2020-04-09 | remove nogo exemption for machine_arm64_unsafe.go | Bin Lu | |
Minimize the use of unsafe. Signed-off-by: Bin Lu <bin.lu@arm.com> | |||
2020-04-08 | Move pagetables.limitPCID to arch-specific file. | Haibo Xu | |
X86 provide 12 bits for PCID while arm64 support 8/16 bits ASID. Signed-off-by: Haibo Xu <haibo.xu@arm.com> Change-Id: I0bd9236e44e6b6c4c88eb6e9adc5ac27b918bf6c | |||
2020-04-06 | Merge release-20200323.0-71-g7482902 (automated) | gVisor bot | |
2020-04-01 | Merge release-20200323.0-49-g4e6a1a5 (automated) | gVisor bot | |
2020-04-01 | Automated rollback of changelist 303799678 | Adin Scannell | |
PiperOrigin-RevId: 304221302 | |||
2020-04-01 | Merge release-20200323.0-48-gdb79175 (automated) | gVisor bot | |
2020-04-01 | Fix 386 build tags | Michael Pratt | |
The build tag for 32-bit x86 is 386, not i386. Updates #2298 PiperOrigin-RevId: 304206373 | |||
2020-03-30 | Merge release-20200219.0-259-g3fac85d (automated) | gVisor bot | |
2020-03-30 | kvm: handle exit reasons even under EINTR. | Adin Scannell | |
In the case of other signals (preemption), inject a normal bounce and defer the signal until the vCPU has been returned from guest mode. PiperOrigin-RevId: 303799678 | |||
2020-03-26 | Merge release-20200219.0-238-g7aa388c (automated) | gVisor bot | |
2020-03-26 | Merge pull request #1986 from lubinszARM:pr_ring0_clean_1 | gVisor bot | |
PiperOrigin-RevId: 303105826 |