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2020-11-18Merge release-20201109.0-74-gc978ab047 (automated)gVisor bot
2020-11-18Merge pull request #4791 from lubinszARM:pr_pt_uppergVisor bot
PiperOrigin-RevId: 343130667
2020-11-18Merge release-20201109.0-66-gee6dd8cb9 (automated)gVisor bot
2020-11-17Merge pull request #4840 from lubinszARM:pr_fpsimd_1gVisor bot
PiperOrigin-RevId: 343000335
2020-11-17Merge release-20201109.0-58-gc1e1e7a9a (automated)gVisor bot
2020-11-17arm64 kvm: optimize all fpsimd related codeRobin Luk
Optimize and bug fix all fpsimd related code. Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
2020-11-17arm64 kvm: add the processing functions for all el0/el1 exceptionsRobin Luk
I added 2 unified processing functions for all exceptions of el/el0 Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
2020-11-12arm64 kvm bug fix: pagetables_test & kvm_test failed due to upper-shared-pt ↵Bin Lu
feature Signed-off-by: Robin Luk <lubin.lu@alibaba-inc.com>
2020-11-09Merge release-20201030.0-56-gd4e0b829e (automated)gVisor bot
2020-11-09Merge pull request #4683 from lemin9538:lemin_fpsmid_fixgVisor bot
PiperOrigin-RevId: 341445910
2020-11-03Merge release-20201027.0-60-g861c11bfa (automated)gVisor bot
2020-11-03Merge pull request #3617 from laijs:upperhalfgVisor bot
PiperOrigin-RevId: 340484823
2020-11-03Merge release-20201027.0-57-g0e96f8065 (automated)gVisor bot
2020-11-03arm64 kvm: inject sError to trigger sigbuslubinszARM
Use an sErr injection to trigger sigbus when we receive EFAULT from the run ioctl. After applying this patch, mmap_test_runsc_kvm will be passed on Arm64. Signed-off-by: Bin Lu <bin.lu@arm.com> COPYBARA_INTEGRATE_REVIEW=https://github.com/google/gvisor/pull/4542 from lubinszARM:pr_kvm_mmap_1 f81bd42466d1d60a581e5fb34de18b78878c68c1 PiperOrigin-RevId: 340461239
2020-11-03kvm: share upper halves among all pagtablesLai Jiangshan
Fixes: #509 Signed-off-by: Lai Jiangshan <jiangshan.ljs@antfin.com> Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
2020-10-30Merge release-20201019.0-110-gc94bf137d (automated)gVisor bot
2020-10-30Merge pull request #4564 from zhlhahaha:1981gVisor bot
PiperOrigin-RevId: 339921446
2020-10-29arm64: fix the fpsmid context save/restore issueMin Le
current when save fpsmid register is using following instruction: # FMOVD Fx, 16*1(R0) this instruction will compiled to: # str Dx, [x0, #16] Dx is 64bit fp register not 128bit, then upper 64bit data will be lossed, this will cause application meet many random crash issue. need use 128bit register Vx or Q0 to save and restore the fpsmid context. Signed-off-by: Min Le <lemin.lm@antgroup.com>
2020-10-28Merge release-20201019.0-92-gd20ef61a8 (automated)gVisor bot
2020-10-28Merge pull request #4630 from lemin9538:lemin_arm64_devgVisor bot
PiperOrigin-RevId: 339540747
2020-10-28Merge release-20201019.0-81-g5fe886ab6 (automated)gVisor bot
2020-10-28arm64: need to restore the sentry's TLS when in EL1Min Le
Signed-off-by: Min Le <lemin.lm@antgroup.com>
2020-10-22arm64 kvm: added the implementation of setSystemTimeLegacy()Bin Lu
I have added support for setSystemTimeLegacy() by setting cntvoff. With this pr, TestRdtsc and other kvm syscall test cases(nanosleep, wait...) can be passed on Arm64. TO-DO: Add precise synchronization to KVM for Arm64. Reference PR: https://github.com/google/gvisor/pull/4397 Signed-off-by: Bin Lu <bin.lu@arm.com>
2020-10-21Merge release-20201019.0-22-g1b2097f84 (automated)gVisor bot
2020-10-21Merge pull request #4535 from lubinszARM:pr_kvm_exec_binary_1gVisor bot
PiperOrigin-RevId: 338321125
2020-10-20Merge release-20201005.0-111-gd45d57f49 (automated)gVisor bot
2020-10-20Merge pull request #4524 from lemin9538:lemin_arm64gVisor bot
PiperOrigin-RevId: 338126491
2020-10-20ARM64 KVM: bad regs.Sp return SIGSEGVHoward Zhang
Consistent with the linux kernel, bad regs.Sp return SIGSEGV Signed-off-by: Howard Zhang <howard.zhang@arm.com>
2020-10-18arm64 kvm: handle exception from accessing undefined instructionBin Lu
Consistent with the linux approach, we will produce a sigill to handle el0_undef. After applying this patch, exec_binary_test_runsc_kvm will be passed on Arm64. Signed-off-by: Bin Lu <bin.lu@arm.com>
2020-10-16Merge release-20201005.0-92-gb491712e1 (automated)gVisor bot
2020-10-16Merge pull request #4387 from lubinszARM:pr_tls_host_sentry_1gVisor bot
PiperOrigin-RevId: 337544656
2020-10-15arm64: the ASID offset of TTBR register is 48Min Le
Signed-off-by: Min Le <lemin.lm@antgroup.com>
2020-10-13Merge release-20200928.0-113-g7eeeff426 (automated)gVisor bot
2020-10-13Merge pull request #4482 from lemin9538:lemin_arm64gVisor bot
PiperOrigin-RevId: 336976081
2020-10-13Merge pull request #4386 from lubinszARM:pr_testutil_tls_usrgVisor bot
PiperOrigin-RevId: 336970511
2020-10-13Merge release-20200928.0-107-gb99f15e06 (automated)gVisor bot
2020-10-13Merge pull request #4374 from lubinszARM:pr_ffmpeg_kvm_01gVisor bot
PiperOrigin-RevId: 336962937
2020-10-13Merge release-20200928.0-101-gd9b32efb3 (automated)gVisor bot
2020-10-13Avoid excessive Tgkill and wait operations.Adin Scannell
The required states may simply not be observed by the thread running bounce, so track guest and user generations to ensure that at least one of the desired state transitions happens. Fixes #3532 PiperOrigin-RevId: 336908216
2020-10-12Merge release-20200928.0-93-g93bc0777b (automated)gVisor bot
2020-10-12Merge pull request #4072 from adamliyi:droppt_fixgVisor bot
PiperOrigin-RevId: 336719900
2020-10-11arm64 kvm: add tls-usr supportBin Lu
The tls of guest-el1-sentry and host-el0-sentry may be different on Arm64. I added a solution for it. Signed-off-by: Bin Lu <bin.lu@arm.com>
2020-10-10arm64: set DZE bit to make EL0 can use DC ZVAMin Le
Signed-off-by: Min Le <lemin.lm@antgroup.com>
2020-10-09Merge release-20200928.0-86-ga0ffc84ad (automated)gVisor bot
2020-10-09platform/kvm: remove the unused fieldAndrei Vagin
PiperOrigin-RevId: 336366624
2020-10-09Merge release-20200928.0-84-g6df400dfb (automated)gVisor bot
2020-10-09Merge pull request #4040 from lemin9538:lemin_arm64gVisor bot
PiperOrigin-RevId: 336362818
2020-10-08arm64: the mair_el1 value is wrongMin Le
the correct value needed is 0xbbff440c0400 but the const defined is 0x000000000000ffc0 due to the operator error in _MT_EL1_INIT, both kernel and user space memory attribute should be Normal memory not DEVICE_nGnRE Signed-off-by: Min Le <lemin.lm@antgroup.com>
2020-10-07Merge release-20200928.0-64-gb89e43e20 (automated)gVisor bot
2020-10-07Merge pull request #4376 from lubinszARM:pr_usr_tls_newgVisor bot
PiperOrigin-RevId: 335930035
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