diff options
| -rw-r--r-- | WORKSPACE | 14 | ||||
| -rw-r--r-- | benchmarks/workloads/ruby_template/BUILD | 1 | ||||
| -rw-r--r-- | pkg/cpuid/cpuid_arm64.go | 77 | ||||
| -rw-r--r-- | test/syscalls/linux/inotify.cc | 9 |
4 files changed, 63 insertions, 38 deletions
@@ -4,19 +4,19 @@ load("@bazel_tools//tools/build_defs/repo:git.bzl", "git_repository") # Load go bazel rules and gazelle. http_archive( name = "io_bazel_rules_go", - sha256 = "b27e55d2dcc9e6020e17614ae6e0374818a3e3ce6f2024036e688ada24110444", + sha256 = "f99a9d76e972e0c8f935b2fe6d0d9d778f67c760c6d2400e23fc2e469016e2bd", urls = [ - "https://storage.googleapis.com/bazel-mirror/github.com/bazelbuild/rules_go/releases/download/v0.21.0/rules_go-v0.21.0.tar.gz", - "https://github.com/bazelbuild/rules_go/releases/download/v0.21.0/rules_go-v0.21.0.tar.gz", + "https://storage.googleapis.com/bazel-mirror/github.com/bazelbuild/rules_go/releases/download/v0.21.2/rules_go-v0.21.2.tar.gz", + "https://github.com/bazelbuild/rules_go/releases/download/v0.21.2/rules_go-v0.21.2.tar.gz", ], ) http_archive( name = "bazel_gazelle", - sha256 = "86c6d481b3f7aedc1d60c1c211c6f76da282ae197c3b3160f54bd3a8f847896f", + sha256 = "d8c45ee70ec39a57e7a05e5027c32b1576cc7f16d9dd37135b0eddde45cf1b10", urls = [ - "https://storage.googleapis.com/bazel-mirror/github.com/bazelbuild/bazel-gazelle/releases/download/v0.19.1/bazel-gazelle-v0.19.1.tar.gz", - "https://github.com/bazelbuild/bazel-gazelle/releases/download/v0.19.1/bazel-gazelle-v0.19.1.tar.gz", + "https://storage.googleapis.com/bazel-mirror/github.com/bazelbuild/bazel-gazelle/releases/download/v0.20.0/bazel-gazelle-v0.20.0.tar.gz", + "https://github.com/bazelbuild/bazel-gazelle/releases/download/v0.20.0/bazel-gazelle-v0.20.0.tar.gz", ], ) @@ -25,7 +25,7 @@ load("@io_bazel_rules_go//go:deps.bzl", "go_rules_dependencies", "go_register_to go_rules_dependencies() go_register_toolchains( - go_version = "1.13.6", + go_version = "1.13.7", nogo = "@//:nogo", ) diff --git a/benchmarks/workloads/ruby_template/BUILD b/benchmarks/workloads/ruby_template/BUILD index 59443b14a..72ed9403d 100644 --- a/benchmarks/workloads/ruby_template/BUILD +++ b/benchmarks/workloads/ruby_template/BUILD @@ -15,5 +15,4 @@ pkg_tar( "index.erb", "main.rb", ], - strip_prefix = "third_party/gvisor/benchmarks/workloads/ruby_template", ) diff --git a/pkg/cpuid/cpuid_arm64.go b/pkg/cpuid/cpuid_arm64.go index 6d71290c9..08381c1c0 100644 --- a/pkg/cpuid/cpuid_arm64.go +++ b/pkg/cpuid/cpuid_arm64.go @@ -36,78 +36,98 @@ import ( // Currently, only the HWCAP bits are supported. const ( - // Single and double precision float point types. + // ARM64FeatureFP indicates support for single and double precision + // float point types. ARM64FeatureFP Feature = iota - // Advanced SIMD with single and double precision - // float point arithmetic. + // ARM64FeatureASIMD indicates support for Advanced SIMD with single + // and double precision float point arithmetic. ARM64FeatureASIMD - // The generic timer is configured to generate - // events at a frequency of approximately 100KHz. + // ARM64FeatureEVTSTRM indicates support for the generic timer + // configured to generate events at a frequency of approximately + // 100KHz. ARM64FeatureEVTSTRM - // AES instructions(AESE/AESD/AESMC/AESIMC). + // ARM64FeatureAES indicates support for AES instructions + // (AESE/AESD/AESMC/AESIMC). ARM64FeatureAES - // AES instructions(PMULL/PMULL2). + // ARM64FeaturePMULL indicates support for AES instructions + // (PMULL/PMULL2). ARM64FeaturePMULL - // SHA1 instructions(SHA1C/SHA1P/SHA1M etc). + // ARM64FeatureSHA1 indicates support for SHA1 instructions + // (SHA1C/SHA1P/SHA1M etc). ARM64FeatureSHA1 - // SHA2 instructions(SHA256H/SHA256H2/SHA256SU0 etc). + // ARM64FeatureSHA2 indicates support for SHA2 instructions + // (SHA256H/SHA256H2/SHA256SU0 etc). ARM64FeatureSHA2 - // CRC32 instructions(CRC32B/CRC32H/CRC32W etc). + // ARM64FeatureCRC32 indicates support for CRC32 instructions + // (CRC32B/CRC32H/CRC32W etc). ARM64FeatureCRC32 - // Atomic instructions(LDADD/LDCLR/LDEOR/LDSET etc). + // ARM64FeatureATOMICS indicates support for atomic instructions + // (LDADD/LDCLR/LDEOR/LDSET etc). ARM64FeatureATOMICS - // Half precision float point arithmetic. + // ARM64FeatureFPHP indicates support for half precision float point + // arithmetic. ARM64FeatureFPHP - // ASIMD with half precision float point arithmetic. + // ARM64FeatureASIMDHP indicates support for ASIMD with half precision + // float point arithmetic. ARM64FeatureASIMDHP - // EL0 access to certain ID registers is available. + // ARM64FeatureCPUID indicates support for EL0 access to certain ID + // registers is available. ARM64FeatureCPUID - // SQRDMLAH and SQRDMLSH instructions implemented. + // ARM64FeatureASIMDRDM indicates support for SQRDMLAH and SQRDMLSH + // instructions. ARM64FeatureASIMDRDM - // The FJCVTZS instruction is implemented. + // ARM64FeatureJSCVT indicates support for the FJCVTZS instruction. ARM64FeatureJSCVT - // The FCMLA and FCADD instructions are implemented. + // ARM64FeatureFCMA indicates support for the FCMLA and FCADD + // instructions. ARM64FeatureFCMA - // The LDAPRB/LDAPRH/LDAPR instructions are implemented. + // ARM64FeatureLRCPC indicates support for the LDAPRB/LDAPRH/LDAPR + // instructions. ARM64FeatureLRCPC - // DC instruction(DC CVAP) supported. + // ARM64FeatureDCPOP indicates support for DC instruction (DC CVAP). ARM64FeatureDCPOP - // SHA3 instructions(EOR3/RAX1/XAR/BCAX) implemented. + // ARM64FeatureSHA3 indicates support for SHA3 instructions + // (EOR3/RAX1/XAR/BCAX). ARM64FeatureSHA3 - // SM3 instructions(SM3SS1/SM3TT1A/SM3TT1B) implemented. + // ARM64FeatureSM3 indicates support for SM3 instructions + // (SM3SS1/SM3TT1A/SM3TT1B). ARM64FeatureSM3 - // SM4 instructions(SM4E/SM4EKEY) implemented. + // ARM64FeatureSM4 indicates support for SM4 instructions + // (SM4E/SM4EKEY). ARM64FeatureSM4 - // Dot Product instructions(UDOT/SDOT) implemented. + // ARM64FeatureASIMDDP indicates support for dot product instructions + // (UDOT/SDOT). ARM64FeatureASIMDDP - // SHA2 instructions(SHA512H/SHA512H2/SHA512SU0) implemented. + // ARM64FeatureSHA512 indicates support for SHA2 instructions + // (SHA512H/SHA512H2/SHA512SU0). ARM64FeatureSHA512 - // Scalable Vector Extension implemented. + // ARM64FeatureSVE indicates support for Scalable Vector Extension. ARM64FeatureSVE - // FMLAL and FMLSL instructions are implemented. + // ARM64FeatureASIMDFHM indicates support for FMLAL and FMLSL + // instructions. ARM64FeatureASIMDFHM ) @@ -237,8 +257,9 @@ func (fs *FeatureSet) HasFeature(feature Feature) bool { return fs.Set[feature] } -// UseXsaveopt returns true if 'fs' supports the "xsaveopt" instruction. -// Noop on arm64. +// UseXsave returns true if 'fs' supports the "xsave" instruction. +// +// Irrelevant on arm64. func (fs *FeatureSet) UseXsave() bool { return false } diff --git a/test/syscalls/linux/inotify.cc b/test/syscalls/linux/inotify.cc index fdef646eb..0e13ad190 100644 --- a/test/syscalls/linux/inotify.cc +++ b/test/syscalls/linux/inotify.cc @@ -1055,9 +1055,9 @@ TEST(Inotify, ChmodGeneratesAttribEvent_NoRandomSave) { const TempPath file1 = ASSERT_NO_ERRNO_AND_VALUE(TempPath::CreateFileIn(root.path())); - const FileDescriptor root_fd = + FileDescriptor root_fd = ASSERT_NO_ERRNO_AND_VALUE(Open(root.path(), O_RDONLY)); - const FileDescriptor file1_fd = + FileDescriptor file1_fd = ASSERT_NO_ERRNO_AND_VALUE(Open(file1.path(), O_RDWR)); FileDescriptor fd = ASSERT_NO_ERRNO_AND_VALUE(InotifyInit1(IN_NONBLOCK)); @@ -1091,6 +1091,11 @@ TEST(Inotify, ChmodGeneratesAttribEvent_NoRandomSave) { ASSERT_THAT(fchmodat(root_fd.get(), file1_basename.c_str(), S_IWGRP, 0), SyscallSucceeds()); verify_chmod_events(); + + // Make sure the chmod'ed file descriptors are destroyed before DisableSave + // is destructed. + root_fd.reset(); + file1_fd.reset(); } TEST(Inotify, TruncateGeneratesModifyEvent) { |