diff options
| author | Nicolas Lacasse <nlacasse@google.com> | 2019-04-29 14:03:04 -0700 |
|---|---|---|
| committer | Shentubot <shentubot@google.com> | 2019-04-29 14:04:14 -0700 |
| commit | f4ce43e1f426148d99c28c1b0e5c43ddda17a8cb (patch) | |
| tree | ef64d18350874742742599c8b059b333eb060920 /vdso | |
| parent | 38e627644756400413fffe7222cdd5200dc4eccf (diff) | |
Allow and document bug ids in gVisor codebase.
PiperOrigin-RevId: 245818639
Change-Id: I03703ef0fb9b6675955637b9fe2776204c545789
Diffstat (limited to 'vdso')
| -rw-r--r-- | vdso/cycle_clock.h | 2 | ||||
| -rw-r--r-- | vdso/vdso_amd64.lds | 2 | ||||
| -rw-r--r-- | vdso/vdso_arm64.lds | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/vdso/cycle_clock.h b/vdso/cycle_clock.h index 26d6690c0..309e07a3f 100644 --- a/vdso/cycle_clock.h +++ b/vdso/cycle_clock.h @@ -23,7 +23,7 @@ namespace vdso { #if __x86_64__ -// TODO: The appropriate barrier instruction to use with rdtsc on +// TODO(b/74613497): The appropriate barrier instruction to use with rdtsc on // x86_64 depends on the vendor. Intel processors can use lfence but AMD may // need mfence, depending on MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT. diff --git a/vdso/vdso_amd64.lds b/vdso/vdso_amd64.lds index 166779931..e2615ae9e 100644 --- a/vdso/vdso_amd64.lds +++ b/vdso/vdso_amd64.lds @@ -56,7 +56,7 @@ SECTIONS { .altinstr_replacement : { *(.altinstr_replacement) } /* - * TODO: Remove this alignment? Then the VDSO would fit + * TODO(gvisor.dev/issue/157): Remove this alignment? Then the VDSO would fit * in a single page. */ . = ALIGN(0x1000); diff --git a/vdso/vdso_arm64.lds b/vdso/vdso_arm64.lds index 19f8efa01..469185468 100644 --- a/vdso/vdso_arm64.lds +++ b/vdso/vdso_arm64.lds @@ -59,7 +59,7 @@ SECTIONS { .altinstr_replacement : { *(.altinstr_replacement) } /* - * TODO: Remove this alignment? Then the VDSO would fit + * TODO(gvisor.dev/issue/157): Remove this alignment? Then the VDSO would fit * in a single page. */ . = ALIGN(0x1000); |