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authorBin Lu <bin.lu@arm.com>2020-09-10 02:47:10 -0400
committerBin Lu <bin.lu@arm.com>2020-09-10 02:47:13 -0400
commit6d688347791526e2a1101333ccc7a410735cf31a (patch)
treee93a14b20c356a3044bf06eb6b66cfed4a1ecf2d /test/runtimes
parent1ab097b08fc16d67b90f094a4316883c289ef77f (diff)
arm64:place an SB sequence following an ERET instruction
Some CPUs(eg: ampere-emag) can speculate past an ERET instruction and potentially perform speculative accesses to memory before processing the exception return. Since the register state is often controlled by a lower privilege level at the point of an ERET, this could potentially be used as part of a side-channel attack. Signed-off-by: Bin Lu <bin.lu@arm.com>
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