diff options
| author | Bin Lu <bin.lu@arm.com> | 2020-07-30 03:42:46 -0400 |
|---|---|---|
| committer | Bin Lu <bin.lu@arm.com> | 2020-07-30 03:44:23 -0400 |
| commit | bb25c9611ba9cb12ab42b08a3a91a095b6f7c824 (patch) | |
| tree | 1be32184cdb9e66050984a4e27ee2debf6877a8a /pkg | |
| parent | 4cd4759238655e35c8dc63723f4e55014b5ea9ea (diff) | |
add usr-tls test cases for Arm64
Signed-off-by: Bin Lu <bin.lu@arm.com>
Diffstat (limited to 'pkg')
| -rw-r--r-- | pkg/sentry/platform/kvm/testutil/testutil_arm64.go | 4 | ||||
| -rw-r--r-- | pkg/sentry/platform/kvm/testutil/testutil_arm64.s | 14 |
2 files changed, 14 insertions, 4 deletions
diff --git a/pkg/sentry/platform/kvm/testutil/testutil_arm64.go b/pkg/sentry/platform/kvm/testutil/testutil_arm64.go index ca902c8c1..4dad877ba 100644 --- a/pkg/sentry/platform/kvm/testutil/testutil_arm64.go +++ b/pkg/sentry/platform/kvm/testutil/testutil_arm64.go @@ -56,5 +56,9 @@ func CheckTestRegs(regs *arch.Registers, full bool) (err error) { err = addRegisterMismatch(err, fmt.Sprintf("R%d", i), regs.Regs[i], need) } } + // Check tls. + if need := ^uint64(11); regs.TPIDR_EL0 != need { + err = addRegisterMismatch(err, "tpdir_el0", regs.TPIDR_EL0, need) + } return } diff --git a/pkg/sentry/platform/kvm/testutil/testutil_arm64.s b/pkg/sentry/platform/kvm/testutil/testutil_arm64.s index 07658144e..6caf7282d 100644 --- a/pkg/sentry/platform/kvm/testutil/testutil_arm64.s +++ b/pkg/sentry/platform/kvm/testutil/testutil_arm64.s @@ -52,6 +52,8 @@ start: TEXT ·FloatingPointWorks(SB),NOSPLIT,$0-8 NO_LOCAL_POINTERS + // gc will touch fpsimd, so we should test it. + // such as in <runtime.deductSweepCredit>. FMOVD $(9.9), F0 MOVD $SYS_GETPID, R8 // getpid SVC @@ -102,11 +104,15 @@ isNaN: TEXT ·TwiddleRegsSyscall(SB),NOSPLIT,$0 TWIDDLE_REGS() + MSR R10, TPIDR_EL0 + // Trapped in el0_svc. SVC RET // never reached TEXT ·TwiddleRegsFault(SB),NOSPLIT,$0 - TWIDDLE_REGS() - // Branch to Register branches unconditionally to an address in <Rn>. - JMP (R4) // <=> br x4, must fault - RET // never reached + TWIDDLE_REGS() + MSR R10, TPIDR_EL0 + // Trapped in el0_ia. + // Branch to Register branches unconditionally to an address in <Rn>. + JMP (R6) // <=> br x6, must fault + RET // never reached |