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| author | Michael Pratt <mpratt@google.com> | 2019-08-26 14:45:25 -0700 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2019-08-26 14:47:05 -0700 |
| commit | 904b1569627f2b5dc2d95c64872572f287d8b77c (patch) | |
| tree | e0de18495f62b130ac066d807d2ee70a09e9d1c9 /pkg/tcpip/checker/BUILD | |
| parent | baf4d8aaca520255d52627779ada2be56be7f861 (diff) | |
Add support for Intel cache CPUID leafs
This exposes L1, L2, etc. cache sizes, cache line size, etc.
Across S/R, everything except cache line size can differ from the host. This is
because cache line size is critical for correct use of CLFLUSH / CLFLUSHOPT,
but as far as I know, the other cache parameters can only affect performance,
not correctness.
AMD uses different leafs for cache information, which are not yet supported.
fail. There are no known cases of cache line size other than 64 in the fleet.
PiperOrigin-RevId: 265544786
Diffstat (limited to 'pkg/tcpip/checker/BUILD')
0 files changed, 0 insertions, 0 deletions