diff options
| author | gVisor bot <gvisor-bot@google.com> | 2020-07-27 22:50:33 +0000 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2020-07-27 22:50:33 +0000 |
| commit | a724f8961639b7b3e155bbcd541fb1bfd7edd083 (patch) | |
| tree | ad88840e596a1a047236d9f2e1004b4d1d7fec44 /pkg/sentry/platform | |
| parent | c31eac6d5c6b646c07be914b6a51968fb2de6cc8 (diff) | |
| parent | b0eafc74544c4fdf4ce36761eeb86a65fa65a712 (diff) | |
Merge release-20200622.1-245-gb0eafc745 (automated)
Diffstat (limited to 'pkg/sentry/platform')
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_impl_arm64.s | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/pkg/sentry/platform/ring0/entry_impl_arm64.s b/pkg/sentry/platform/ring0/entry_impl_arm64.s index 0f8126463..7dffa6275 100644 --- a/pkg/sentry/platform/ring0/entry_impl_arm64.s +++ b/pkg/sentry/platform/ring0/entry_impl_arm64.s @@ -112,6 +112,12 @@ #define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT) +// cntkctl_el1: counter-timer kernel control register el1. +#define CNTKCTL_EL0PCTEN 1 << 0 +#define CNTKCTL_EL0VCTEN 1 << 1 + +#define CNTKCTL_EL1_DEFAULT (CNTKCTL_EL0PCTEN | CNTKCTL_EL0VCTEN) + // Saves a register set. // // This is a macro because it may need to executed in contents where a stack is @@ -573,6 +579,9 @@ TEXT ·Start(SB),NOSPLIT,$0 MOVD $SCTLR_EL1_DEFAULT, R1 MSR R1, SCTLR_EL1 + MOVD $CNTKCTL_EL1_DEFAULT, R1 + MSR R1, CNTKCTL_EL1 + MOVD R8, RSV_REG ORR $0xffff000000000000, RSV_REG, RSV_REG WORD $0xd518d092 //MSR R18, TPIDR_EL1 |