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| author | gVisor bot <gvisor-bot@google.com> | 2019-12-26 21:55:07 +0000 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2019-12-26 21:55:07 +0000 |
| commit | 79a5db3009bbee6069e28340b0e9c411ac3621a6 (patch) | |
| tree | 6618e68fd980e02431dd02aa0a7dbf0b37d1892a /pkg/sentry/platform | |
| parent | 464ba7585f54fa170daa9cdadd0bf9d27e8b82cc (diff) | |
| parent | 7b5a59d5038df65a3d5ebb6a24e6b8a2aaa898ab (diff) | |
Merge release-20191213.0-51-g7b5a59d (automated)
Diffstat (limited to 'pkg/sentry/platform')
| -rwxr-xr-x | pkg/sentry/platform/ring0/entry_impl_arm64.s | 4 | ||||
| -rwxr-xr-x | pkg/sentry/platform/ring0/lib_arm64.s | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/pkg/sentry/platform/ring0/entry_impl_arm64.s b/pkg/sentry/platform/ring0/entry_impl_arm64.s index 80df36027..d7910a8df 100755 --- a/pkg/sentry/platform/ring0/entry_impl_arm64.s +++ b/pkg/sentry/platform/ring0/entry_impl_arm64.s @@ -618,6 +618,10 @@ TEXT ·Vectors(SB),NOSPLIT,$0 B ·El0_error_invalid(SB) nop31Instructions() + // The exception-vector-table is required to be 11-bits aligned. + // Please see Linux source code as reference: arch/arm64/kernel/entry.s. + // For gvisor, I defined it as 4K in length, filled the 2nd 2K part with NOPs. + // So that, I can safely move the 1st 2K part into the address with 11-bits alignment. WORD $0xd503201f //nop nop31Instructions() WORD $0xd503201f diff --git a/pkg/sentry/platform/ring0/lib_arm64.s b/pkg/sentry/platform/ring0/lib_arm64.s index 1c9171004..0e6a6235b 100755 --- a/pkg/sentry/platform/ring0/lib_arm64.s +++ b/pkg/sentry/platform/ring0/lib_arm64.s @@ -12,12 +12,15 @@ // See the License for the specific language governing permissions and // limitations under the License. +#include "funcdata.h" +#include "textflag.h" + TEXT ·CPACREL1(SB),NOSPLIT,$0-8 WORD $0xd5381041 // MRS CPACR_EL1, R1 MOVD R1, ret+0(FP) RET -TEXT ·FPCR(SB),NOSPLIT,$0-8 +TEXT ·GetFPCR(SB),NOSPLIT,$0-8 WORD $0xd53b4201 // MRS NZCV, R1 MOVD R1, ret+0(FP) RET @@ -27,7 +30,7 @@ TEXT ·GetFPSR(SB),NOSPLIT,$0-8 MOVD R1, ret+0(FP) RET -TEXT ·FPCR(SB),NOSPLIT,$0-8 +TEXT ·SetFPCR(SB),NOSPLIT,$0-8 MOVD addr+0(FP), R1 WORD $0xd51b4201 // MSR R1, NZCV RET |