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| author | Min Le <lemin.lm@antgroup.com> | 2020-09-22 15:52:41 +0800 |
|---|---|---|
| committer | Min Le <lemin.lm@antgroup.com> | 2020-09-22 17:19:34 +0800 |
| commit | a38f1d145797b307afc34985533f3b9208eacc7d (patch) | |
| tree | 7803a692fdbec72718973dc59403e04938659f59 /pkg/sentry/platform | |
| parent | 742e58b873dbb8d3c14b2e40f212df90ec837671 (diff) | |
arm64: set SCTLR_UCI bit in SCTLR_EL1
some application such as openjdk will excute
DC CVAU at el0, if SCTLR_UCI is not set, it
will trap to EL1 which will cause panic.
Signed-off-by: Min Le <lemin.lm@antgroup.com>
Diffstat (limited to 'pkg/sentry/platform')
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_arm64.s | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/pkg/sentry/platform/ring0/entry_arm64.s b/pkg/sentry/platform/ring0/entry_arm64.s index 5f63cbd45..106762665 100644 --- a/pkg/sentry/platform/ring0/entry_arm64.s +++ b/pkg/sentry/platform/ring0/entry_arm64.s @@ -47,8 +47,9 @@ #define SCTLR_C 1 << 2 #define SCTLR_I 1 << 12 #define SCTLR_UCT 1 << 15 +#define SCTLR_UCI 1 << 26 -#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT) +#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT | SCTLR_UCI) // cntkctl_el1: counter-timer kernel control register el1. #define CNTKCTL_EL0PCTEN 1 << 0 |