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| author | gVisor bot <gvisor-bot@google.com> | 2020-07-13 20:26:48 +0000 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2020-07-13 20:26:48 +0000 |
| commit | a47ef26cb1325b0518fa06dfc697987fed2f7b4c (patch) | |
| tree | b5ea455c2b1cf362dede66336ac7e721ac02bbb0 /pkg/sentry/platform/ring0 | |
| parent | 2384bead1b850dcca2138c591355878117dc2f54 (diff) | |
| parent | 505b4f5e5f84f5379720966b6b5adaf00178690c (diff) | |
Merge release-20200622.1-100-g505b4f5e5 (automated)
Diffstat (limited to 'pkg/sentry/platform/ring0')
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_impl_arm64.s | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/pkg/sentry/platform/ring0/entry_impl_arm64.s b/pkg/sentry/platform/ring0/entry_impl_arm64.s index 2a19337d0..0f8126463 100644 --- a/pkg/sentry/platform/ring0/entry_impl_arm64.s +++ b/pkg/sentry/platform/ring0/entry_impl_arm64.s @@ -104,6 +104,14 @@ #define FPEN_ENABLE (FPEN_NOTRAP << FPEN_SHIFT) +// sctlr_el1: system control register el1. +#define SCTLR_M 1 << 0 +#define SCTLR_C 1 << 2 +#define SCTLR_I 1 << 12 +#define SCTLR_UCT 1 << 15 + +#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT) + // Saves a register set. // // This is a macro because it may need to executed in contents where a stack is @@ -560,6 +568,11 @@ TEXT ·kernelExitToEl1(SB),NOSPLIT,$0 // Start is the CPU entrypoint. TEXT ·Start(SB),NOSPLIT,$0 IRQ_DISABLE + + // Init. + MOVD $SCTLR_EL1_DEFAULT, R1 + MSR R1, SCTLR_EL1 + MOVD R8, RSV_REG ORR $0xffff000000000000, RSV_REG, RSV_REG WORD $0xd518d092 //MSR R18, TPIDR_EL1 |