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| author | gVisor bot <gvisor-bot@google.com> | 2020-10-09 21:17:17 +0000 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2020-10-09 21:17:17 +0000 |
| commit | 544dbeba179c4667ca48254ffd3105929c0e8ec8 (patch) | |
| tree | d8f291c55f6024268992e9c7c2ef1bfa1b45ab2d /pkg/sentry/platform/ring0 | |
| parent | c2efbcaa5bb105e652045ee720e8acec1e2bc50d (diff) | |
| parent | 6df400dfb61e2219b1d88dd2aa6be7fbb59d3ab6 (diff) | |
Merge release-20200928.0-84-g6df400dfb (automated)
Diffstat (limited to 'pkg/sentry/platform/ring0')
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_impl_arm64.s | 3 | ||||
| -rw-r--r-- | pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/pkg/sentry/platform/ring0/entry_impl_arm64.s b/pkg/sentry/platform/ring0/entry_impl_arm64.s index a3381b701..af2bdefcb 100644 --- a/pkg/sentry/platform/ring0/entry_impl_arm64.s +++ b/pkg/sentry/platform/ring0/entry_impl_arm64.s @@ -118,8 +118,9 @@ #define SCTLR_C 1 << 2 #define SCTLR_I 1 << 12 #define SCTLR_UCT 1 << 15 +#define SCTLR_UCI 1 << 26 -#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT) +#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT | SCTLR_UCI) // cntkctl_el1: counter-timer kernel control register el1. #define CNTKCTL_EL0PCTEN 1 << 0 diff --git a/pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go b/pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go index 6409d1d91..520161755 100644 --- a/pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go +++ b/pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go @@ -78,7 +78,7 @@ const ( const ( executeDisable = xn - optionMask = 0xfff | 0xfff<<48 + optionMask = 0xfff | 0xffff<<48 protDefault = accessed | shared ) @@ -188,7 +188,7 @@ func (p *PTE) Set(addr uintptr, opts MapOpts) { v |= mtNormal } else { v = v &^ user - v |= mtDevicenGnRE // Strong order for the addresses with ring0.KernelStartAddress. + v |= mtNormal } atomic.StoreUintptr((*uintptr)(p), v) } |