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authorRobin Luk <lubin.lu@antgroup.com>2021-03-26 16:04:28 +0800
committerRobin Luk <lubin.lu@antgroup.com>2021-03-26 16:10:21 +0800
commit72cd22163f9c7fdfafa645b3b6826b185bbbdf76 (patch)
treecec53fc59bfbab898a9686988cb0a7568e27bf48 /pkg/sentry/platform/kvm
parentfbec65fc3f21773cbec3db4aadf27b85e8859448 (diff)
arm64 ring0: don't use inner-sharable to invalidate tlb
It is enough to invalidate the tlb of local vcpu in switch(). TLBI with inner-sharable will invalidate the tlb in other vcpu. Arm64 hardware supports at least 256 pcid, so I think it's ok to set the length of pcid pool to 128. Signed-off-by: Robin Luk <lubin.lu@antgroup.com>
Diffstat (limited to 'pkg/sentry/platform/kvm')
-rw-r--r--pkg/sentry/platform/kvm/machine_arm64.go2
1 files changed, 1 insertions, 1 deletions
diff --git a/pkg/sentry/platform/kvm/machine_arm64.go b/pkg/sentry/platform/kvm/machine_arm64.go
index 2edc9d1b2..2055e61a7 100644
--- a/pkg/sentry/platform/kvm/machine_arm64.go
+++ b/pkg/sentry/platform/kvm/machine_arm64.go
@@ -47,7 +47,7 @@ const (
// Beyond a relatively small number, there are likely few perform
// benefits, since the TLB has likely long since lost any translations
// from more than a few PCIDs past.
- poolPCIDs = 8
+ poolPCIDs = 128
)
func (m *machine) mapUpperHalf(pageTable *pagetables.PageTables) {