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| author | gVisor bot <gvisor-bot@google.com> | 2021-06-12 01:47:48 +0000 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2021-06-12 01:47:48 +0000 |
| commit | 75fa1f12952875b3125deb542c15d13a430a17c1 (patch) | |
| tree | 1f7a8ea3dd2609f871ec0600cf73a01fbf3e18d0 /pkg/ring0 | |
| parent | 61c7cf465bc5eb394b17a32d3168041f7d1d18ab (diff) | |
| parent | ec6a7ebc75f714e9ac8ae1dc785304661f6e63b4 (diff) | |
Merge release-20210601.0-50-gec6a7ebc7 (automated)
Diffstat (limited to 'pkg/ring0')
| -rw-r--r-- | pkg/ring0/kernel_amd64.go | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/pkg/ring0/kernel_amd64.go b/pkg/ring0/kernel_amd64.go index 41dfd0bf9..f63af8b76 100644 --- a/pkg/ring0/kernel_amd64.go +++ b/pkg/ring0/kernel_amd64.go @@ -254,6 +254,8 @@ func (c *CPU) SwitchToUser(switchOpts SwitchOpts) (vector Vector) { return } +var sentryXCR0 = xgetbv(0) + // start is the CPU entrypoint. // // This is called from the Start asm stub (see entry_amd64.go); on return the @@ -265,24 +267,10 @@ func start(c *CPU) { WriteGS(kernelAddr(c.kernelEntry)) WriteFS(uintptr(c.registers.Fs_base)) - // Initialize floating point. - // - // Note that on skylake, the valid XCR0 mask reported seems to be 0xff. - // This breaks down as: - // - // bit0 - x87 - // bit1 - SSE - // bit2 - AVX - // bit3-4 - MPX - // bit5-7 - AVX512 - // - // For some reason, enabled MPX & AVX512 on platforms that report them - // seems to be cause a general protection fault. (Maybe there are some - // virtualization issues and these aren't exported to the guest cpuid.) - // This needs further investigation, but we can limit the floating - // point operations to x87, SSE & AVX for now. fninit() - xsetbv(0, validXCR0Mask&0x7) + // Need to sync XCR0 with the host, because xsave and xrstor can be + // called from different contexts. + xsetbv(0, sentryXCR0) // Set the syscall target. wrmsr(_MSR_LSTAR, kernelFunc(sysenter)) |