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| author | gVisor bot <gvisor-bot@google.com> | 2021-04-09 17:15:06 -0700 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2021-04-09 17:15:06 -0700 |
| commit | 7420821a7b5fe15f3666bb4971796cd45fc5ff38 (patch) | |
| tree | e589b5c862322dd86a1d0ebee93c0bb5c2710e3b /pkg/ring0/lib_amd64.s | |
| parent | dc8f6c6914747c700a629b7717e45759cf1f7650 (diff) | |
| parent | eb9b8e53a3ef7bb96dcb59a0121fa9ed22f01bfd (diff) | |
Merge pull request #5767 from avagin:mxcsr
PiperOrigin-RevId: 367730917
Diffstat (limited to 'pkg/ring0/lib_amd64.s')
| -rw-r--r-- | pkg/ring0/lib_amd64.s | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/pkg/ring0/lib_amd64.s b/pkg/ring0/lib_amd64.s index 2fe83568a..70a43e79e 100644 --- a/pkg/ring0/lib_amd64.s +++ b/pkg/ring0/lib_amd64.s @@ -198,3 +198,15 @@ TEXT ·rdmsr(SB),NOSPLIT,$0-16 MOVL AX, ret+8(FP) MOVL DX, ret+12(FP) RET + +// stmxcsr reads the MXCSR control and status register. +TEXT ·stmxcsr(SB),NOSPLIT,$0-8 + MOVQ addr+0(FP), SI + STMXCSR (SI) + RET + +// ldmxcsr writes to the MXCSR control and status register. +TEXT ·ldmxcsr(SB),NOSPLIT,$0-8 + MOVQ addr+0(FP), SI + LDMXCSR (SI) + RET |