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authorgVisor bot <gvisor-bot@google.com>2020-03-30 21:43:35 +0000
committergVisor bot <gvisor-bot@google.com>2020-03-30 21:43:35 +0000
commit818c088790ce64ec3cd2149866872e6c3bd60a69 (patch)
treeb11d9207b77ff3a9420d87cfd0e476c37789b9e8 /pkg/cpuid
parentd571e84103e866d2f7348c678020e548d6895de3 (diff)
parent32a133537e61bbceb6a0a16c95815495d8f17a35 (diff)
Merge release-20200219.0-261-g32a1335 (automated)
Diffstat (limited to 'pkg/cpuid')
-rwxr-xr-xpkg/cpuid/cpuid_x86.go7
1 files changed, 6 insertions, 1 deletions
diff --git a/pkg/cpuid/cpuid_x86.go b/pkg/cpuid/cpuid_x86.go
index a0bc55ea1..9abf6914d 100755
--- a/pkg/cpuid/cpuid_x86.go
+++ b/pkg/cpuid/cpuid_x86.go
@@ -235,7 +235,9 @@ const (
X86FeaturePERFCTR_TSC
X86FeaturePERFCTR_LLC
X86FeatureMWAITX
- // ECX[31:30] are reserved.
+ // TODO(b/152776797): Some CPUs set this but it is not documented anywhere.
+ X86FeatureBlock5Bit30
+ _ // ecx bit 31 is reserved.
)
// Block 6 constants are the extended feature bits in
@@ -438,6 +440,9 @@ var x86FeatureParseOnlyStrings = map[Feature]string{
// Block 3.
X86FeaturePREFETCHWT1: "prefetchwt1",
+
+ // Block 5.
+ X86FeatureBlock5Bit30: "block5_bit30",
}
// intelCacheDescriptors describe the caches and TLBs on the system. They are