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authorgVisor bot <gvisor-bot@google.com>2020-07-27 15:46:33 -0700
committergVisor bot <gvisor-bot@google.com>2020-07-27 15:46:33 -0700
commitb0eafc74544c4fdf4ce36761eeb86a65fa65a712 (patch)
treeb5bc6ac7590272461d5612d64eafcc482ca5a716
parent1b2006083cdd9d4f3f1c9f583a8afa66adfdad19 (diff)
parentced5863c4938ab2219331dc88bb3a301c1815918 (diff)
Merge pull request #3201 from lubinszARM:pr_sys64_2
PiperOrigin-RevId: 323456118
-rw-r--r--pkg/sentry/platform/ring0/entry_arm64.s9
1 files changed, 9 insertions, 0 deletions
diff --git a/pkg/sentry/platform/ring0/entry_arm64.s b/pkg/sentry/platform/ring0/entry_arm64.s
index 6ed73699b..9fd02d628 100644
--- a/pkg/sentry/platform/ring0/entry_arm64.s
+++ b/pkg/sentry/platform/ring0/entry_arm64.s
@@ -48,6 +48,12 @@
#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT)
+// cntkctl_el1: counter-timer kernel control register el1.
+#define CNTKCTL_EL0PCTEN 1 << 0
+#define CNTKCTL_EL0VCTEN 1 << 1
+
+#define CNTKCTL_EL1_DEFAULT (CNTKCTL_EL0PCTEN | CNTKCTL_EL0VCTEN)
+
// Saves a register set.
//
// This is a macro because it may need to executed in contents where a stack is
@@ -509,6 +515,9 @@ TEXT ·Start(SB),NOSPLIT,$0
MOVD $SCTLR_EL1_DEFAULT, R1
MSR R1, SCTLR_EL1
+ MOVD $CNTKCTL_EL1_DEFAULT, R1
+ MSR R1, CNTKCTL_EL1
+
MOVD R8, RSV_REG
ORR $0xffff000000000000, RSV_REG, RSV_REG
WORD $0xd518d092 //MSR R18, TPIDR_EL1