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| author | Min Le <lemin.lm@antgroup.com> | 2020-10-10 16:38:34 +0800 |
|---|---|---|
| committer | Min Le <lemin.lm@antgroup.com> | 2020-10-10 16:50:51 +0800 |
| commit | 2ae97b27aa385ddb51c234ec31fb4c4869c0088a (patch) | |
| tree | 87cf4ae937cf23c0f4a130eaf5a70e82d0ae6335 | |
| parent | db36d948fa63ce950d94a5e8e9ebc37956543661 (diff) | |
arm64: set DZE bit to make EL0 can use DC ZVA
Signed-off-by: Min Le <lemin.lm@antgroup.com>
| -rw-r--r-- | pkg/sentry/platform/ring0/entry_arm64.s | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/pkg/sentry/platform/ring0/entry_arm64.s b/pkg/sentry/platform/ring0/entry_arm64.s index 494baaa4d..38eb4d873 100644 --- a/pkg/sentry/platform/ring0/entry_arm64.s +++ b/pkg/sentry/platform/ring0/entry_arm64.s @@ -46,10 +46,11 @@ #define SCTLR_M 1 << 0 #define SCTLR_C 1 << 2 #define SCTLR_I 1 << 12 +#define SCTLR_DZE 1 << 14 #define SCTLR_UCT 1 << 15 #define SCTLR_UCI 1 << 26 -#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT | SCTLR_UCI) +#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT | SCTLR_UCI | SCTLR_DZE) // cntkctl_el1: counter-timer kernel control register el1. #define CNTKCTL_EL0PCTEN 1 << 0 |