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| author | Michael Pratt <mpratt@google.com> | 2020-03-30 14:37:17 -0700 |
|---|---|---|
| committer | gVisor bot <gvisor-bot@google.com> | 2020-03-30 14:38:41 -0700 |
| commit | 32a133537e61bbceb6a0a16c95815495d8f17a35 (patch) | |
| tree | b5fd6ef0c409e5d5de553052440b6345f99e9c95 | |
| parent | e36eccc4b18676e2cb441380d0e4e46f038f638e (diff) | |
Add AMD Rome CPUID flag.
This flag is set on Rome CPUs, but it is not documented.
PiperOrigin-RevId: 303825532
| -rw-r--r-- | pkg/cpuid/cpuid_x86.go | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/pkg/cpuid/cpuid_x86.go b/pkg/cpuid/cpuid_x86.go index a0bc55ea1..9abf6914d 100644 --- a/pkg/cpuid/cpuid_x86.go +++ b/pkg/cpuid/cpuid_x86.go @@ -235,7 +235,9 @@ const ( X86FeaturePERFCTR_TSC X86FeaturePERFCTR_LLC X86FeatureMWAITX - // ECX[31:30] are reserved. + // TODO(b/152776797): Some CPUs set this but it is not documented anywhere. + X86FeatureBlock5Bit30 + _ // ecx bit 31 is reserved. ) // Block 6 constants are the extended feature bits in @@ -438,6 +440,9 @@ var x86FeatureParseOnlyStrings = map[Feature]string{ // Block 3. X86FeaturePREFETCHWT1: "prefetchwt1", + + // Block 5. + X86FeatureBlock5Bit30: "block5_bit30", } // intelCacheDescriptors describe the caches and TLBs on the system. They are |